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1 128 bit x24c00 16 x 8 bit serial e 2 prom ? xicor, inc. 1991, 1995, 1996 patents pending characteristics subject to change without notice 3836-1.5 2/24/99 t2/c1/d0 ns description the x24c00 is a cmos 128 bit serial e 2 prom, inter- nally organized as 16 x 8. the x24c00 features a se rial interface and software protocol allowing operation on a simple two wire bus. xicor e 2 proms are designed and tested for applica- tions requiring extended endurance. inherent data r e- tention is greater than 100 years. the x24c00 is fabricated with xicor?s advanced cmos floating gate technology. features ? 2.7v to 5.5v power supply ? 128 bit serial e 2 prom ? low power cmos ? active current less than 3ma ? standby current less than 50a ? internally organized 16 x 8 ? 2 wire serial interface ? bidirectional data transfer protocol ? byte mode write ? self timed write cycle ? typical write cycle time of 5ms ? push/pull output ? high reliability ? endurance: 100,000 cycles ?data retention: 100 years ? available packages ? 8 - lead msop ?8-lead pdip ? 8 - lead soic functional diagram control logic input/ output buffer scl sda command/address register shift register memory array 3836 fhd f01 pin configuration a pplication n otes an4 ? an12 ? an22 ? an26 ? an32 v cc nc scl sda 3836 fhd f02.1 nc nc nc v ss 1 2 3 4 8 7 6 5 x24c00 msop/dip/soic this x24c00 device has been acquired by ic microsystems from xicor; inc.
2 x24c00 pin descriptions serial clock (scl) the scl input is used to clock all data into and ou t of the device. serial data (sda) sda is a bidirectional pin used to transfer data in to and out of the device. it is a push/pull output and does no t require the use of a pull-up resistor. pin names symbol description nc no connect v ss ground v cc supply voltage sda serial data scl serial clock 3836 pgm t01 device operation the x24c00 supports a bidirectional bus oriented pr o- tocol. the protocol defines any device that sends d ata onto the bus as a transmitter and the receiving dev ice as the receiver. the device controlling the transfer is a master and the device being controlled is the slave . the master will always initiate data transfers and prov ide the clock for both transmit and receive operations. the re- fore, the x24c00 will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are re- served for indicating start and stop conditions. re fer to figures 1 and 2. start condition all commands are preceded by the start condi tion, which is a high to low transition of sda wh en scl is high. the x24c00 continuously monitors the sda and scl lines for the start condition and will not resp ond to any command until this condition has been met. a start may be issued to terminate the input of a c ontrol word or the input of data to be written. this will reset the device and leave it ready to begin a new read or wr ite command. because of the push/pull output, a start cannot be generated while the part is outputting da ta. starts are also inhibited while a write is in progr ess. stop condition the stop condition is a low to high transition of s da when scl is high. the stop condition is used to res et the device during a command or data input sequence and will leave the device in the standby mode. as w ith starts, stops are inhibited when outputting d ata and while a write is in progress. write operation the byte write operation is initiated with a start condition. the start condition is followed by an eight bit con trol byte which consists of a two bit write command (0,1), fo ur address bits, and two ?don?t care? bits (figure 3).
x24c00 3 figure 1. data validity scl sda data stable data change 3836 fhd f03 figure 2 . definition of start and stop conditions scl sda start condition stop condition 3836 fhd f04 figure 3. control byte start c1 c2 a3 a2 a1 a0 xx xx 3836 fhd f05
4 x24c00 read operation the byte read operation is initiated with a start c ondition. the start condition is followed by an eight-bit con trol byte which consists of a two -bit read command (1,0), four address bits, and two ?don?t care? bits. after rece ipt of the control byte the x24c00 will enter the read mod e and transfer data into the shift register from the arra y. this data is shifted out of the device on the next eight scl clocks. at the end of the read, all counters are re set and the x24c00 will enter the standby mode. as with a w rite, the read operation can be interrupted by a start or sto p condition while the command or address is being clo cked in. while clocking data out, starts or stops cannot be generated. during the second don?t care clock cycle, st arts and stops are ignored. the master must free the bus pri or to the end of this clock cycle to allow the x24c00 to begin outputting data (figures 5 and 6). after receipt of the control byte, the x24c00 will enter the write mode and await the data to be written. this d ata is shifted into the device on the next eight scl cl ocks. once eight clocks have been received, the data in t he shift register will be written into the memory arra y. while the write is in progress the x24c00 will not respond to any inputs. at any time prior to clocking in the la st data bit, a stop command or a new start command will terminate the operation. if a start command is give n, the x24c00 will reset all counters and will prepare to clock in the next control byte. if a stop command is give n, the x24c00 will reset all counters and await the next s tart command. at the end of the write the x24c00 will automatical ly reset all counters and enter the standby mod e. (figure 4). figure 4. write sequence 3836 fhd f06 start 0 1 a3 a2 a1 a0 xx xx d7 d6 d5 d4 d3 d2 d1 d0 figure 5. read sequence start 1 0 a3 a2 a1 a0 xx xx d7 d6 d5 d4 d3 d2 d1 d0 3836 fhd f07 6 7 8 1 sda in sck sda out a0 xx xx d7 d6 3836 fhd f08 waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance symbol table figure 6. read cycle timing
x24c00 5 *comment stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and the functional ope ration of the device at these or any other conditions above those indicated in the operational sections of this speci fication is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliab ility. absolute maximum ratings* temperature under bias x24c00 ...................................... ?65c to +13 5c storage temperature ....................... ?65c t o +150c voltage on an y pin with respect to v ss ............................................ ?1v to +7v d.c. output current ............................... .............. 5ma lead temperature (soldering, 10 seconds) .............................. 300c recommended operating cond itions temperature min. max. commercial 0c +70c industrial ?40c +85c military ?55c +125c 3836 pgm t02.1 d.c. operating characteristics (over recommended operating conditions unless other wise specified.) limits symbol parameter min. max. units test co nditions l cc1 v cc supply current read 1 ma scl = vcc x 0.1/vcc x 0.9 i cc2 v cc supply current write 3 levels @ 1mhz, sda = open i sb1 v cc standby current 100 a scl = sda = v cc v cc = 5v 10% i sb2 v cc standby current 50 a scl = sda = v cc v cc = 2.7v i li input leakage current 10 a v in = v ss to v cc i lo output leakage current 10 a v out = v ss to v cc v ll (1) input low voltage ?1 v cc x 0.3 v v ih (1) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 2.1ma v oh output high voltage v cc ? 0.8 v i oh = 1ma 3841 pgm t04.3 capacitance t a = +25c, f = 1mhz, v cc = 5v symbol parameter max. units test conditions c i/o (2) input/output capacitance (sda) 8 pf v i/o = 0v c in (2) input capacitance (scl) 6 pf v in = 0v 3836 pgm t05.1 notes: (1)v il min. and v ih max. are for reference only and are not tested. (2)this parameter is periodically sampled and not 1 00% tested. supply voltage limits x24c00 5v 10% x24c00-3 3v to 5.5v x24c00-2.7 2.7v to 5.5v 3836 pgm t03.1
6 x24c00 symbol parameter min. max. units f scl scl clock frequency 0 1 mhz t aa scl low to sda data out valid 350 ns t buf time the bus must be free before a 500 ns new transmission can start t hd:sta start condition hold time 250 ns t low clock low period 500 ns t high clock high period 500 ns t su:sta start condition setup time 250 ns t hd:dat data in hold time 0 s t su:dat data in setup time 250 ns t r sda and scl rise time 1 s t f sda and scl fall time 300 ns t su:sto stop condition setup time 250 ns t dh data out hold time 50 ns 3836 pgm t07.1 a.c. characteristics (over the recommended operating conditions unless otherwise specified.) read & write cycle limits power - up timing symbol paramet er max. units t pur (3) power-up to read operation 2 ms t puw (3) power-up to write operation 5 ms 3836 pgm t08 a.c. conditions of test input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 3836 pgm t06.1 equivalent a.c. load circuit note: (3) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiat ed. these parameters are periodically sampled and not 100% tested. 3836 fhd f09.2 5v 2.16k 100pf output 3.07k
x24c00 7 bus timing t su:sta t hd:sta t hd:dat t su:dat t low t su:sto t r t buf scl sda in sda out t dh t aa t f t high 3836 fhd f10 write cycle limits symbol parameter min. max. units t wr (4) write cycle time 5 ms 3836 pgm t09 write cycle timing 3836 ill f11.1 sda t wr scl d0 start condtion x24c00 address note: (4)the write cycle time is the time from the initia tion of a write sequence to the end of the internal erase/program cycle. during the write cycle, the x24c00 bus interface circuits are disabl ed, sda is high impedance, and the device does not respond to start conditions.
8 x24c00 packaging information 0.118 0.002 (3.00 0.05) 0.040 0.002 (1.02 0.05) 0.150 (3.81) ref. 0.193 (4.90) ref. 0.030 (0.76) 0.036 (0.91) 0.032 (0.81) 0.007 (0.18) 0.005 (0.13) 0.008 (0.20) 0.004 (0.10) 0.0216 (0.55) 7 typ r 0.014 (0.36) 0.118 0.002 (3.00 0.05) 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.0256 (0.65) typ 8 - lead miniature small outline gull wing package type m note: 1. all dimensions in inches and (millimeters) 3926 ill f49
x24c00 9 3926 fhd f01 note: 1. all dimensions in inches (in parentheses in mil limeters) 2. package dimensions exclude molding flash 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref. pin 1 index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) pin 1 seating plane 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) typ. 0.010 (0.25) 0 15 8 - lead plastic dual in - line package type p half shoulder width on all end pins optional 0.015 (0.38) max. 0.325 (8.25) 0.300 (7.62) packaging information
10 x24c00 packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 ? 8 x 45 3926 fhd f22.1 8 - lead plastic small outline gull wing package type s note: all dimensions in inches (in parentheses in m illimeters) 0.250" 0.050" typical 0.050" typical 0.030" typical 8 places footprint
x24c00 11 blank = 8-lead soic p = 8-lead plastic dip blank = 4.5 to 5.5v, 0c to +70c i = 4.5 to 5.5v, ?40c to +85c m = 4.5 to 5.5v, ?55c to +85c d = 3 to 5.5v, 0c to +70c e = 3 to 5.5v, ?40c to +85c f = 2.7 to 5.5v, 0c to +70c g = 2.7 to 5.5v, ?40c to +85c ordering information part mark convention device v cc range blank = 5v 10% 3 = 3v to 5.5v 2.7 = 2.7v to 5.5v temperature range blank = commercial = 0c to +70c i = industrial = ?40c to +85c m = military = ?55c to +125c package m = 8-lead msop p = 8-lead plastic dip s = 8-lead soic limited warranty devices sold by xicor, inc. are covered by the warranty an d patent indemnification provisions appearing in its ter ms of sale only. xicor, inc. makes no warranty, express, statutory, implied, or by descripti on regarding the information set forth herein or reg arding the freedom of the descri bed devices from patent infringement. xicor, inc. makes no warranty of merchantability or fitness tor any purpose. xicor, i nc. reserves the right to discontinue production and change specifications and prices at any time and without n otice. xicor, inc. as sumes no responsibility for the use of any circuitry ot her than circuitry embodied in a xicor, inc. product. no other circuits, patents, licenses are implied. us. patents xicor products are covered by one or more of the follo wing u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,8 46; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,8 29,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694. foreign patents a nd additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this pro duct should design the system with appropriate error detection and correction, redunda ncy and back-up features to prevent such an occurre nce. xicor?s products are not authorized for use as crit ical components in life support devices or systems. 1. life support devices or systems are devices or s ystems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labe ling, can be reasonab ly expected to result in a significant injury to the user. 2. a critical component is any component of a life su pport device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness. 8 - lead soic/pdip x24c00 x x 8 - lead msop eyww xxx coo = 4.5 to 5.5v, 0c to 70c cood = 3.0 to 5.5v, 0 to 70c g = rohs complaint lead - free package blank = standard package. non lead-free x x x - x x24 c00

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